1. Field of the Invention
The present invention relates to an input circuit, and more particularly to an input circuit provided in a semiconductor integrated circuit to which a scan path test method is applied.
2. Description of the Related Art
A scan path test method is known as a failure diagnostic method of a semiconductor integrated circuit. In the scan path test method, a scan path configured of shift registers is formed by connecting, in series, flip-flops present in the semiconductor integrated circuit, and data in the flip-flops are sequentially shifted out through the scan path during the failure diagnosis.
In a block such as a storage device included in the semiconductor integrated circuit, a latch circuit captures and holds an input signal. To apply the scan path test method, as a method to incorporate the latch circuit in a scan path so as to be observable, it is known to replace the latch circuit with a scan flip-flop circuit having a shift function (e.g., Unexamined Japanese Patent Publication No. H10-242809).